Anisina
commented
4 years ago Hi,
I had a look on your design and created a branch "ycma_lab02" for my test running. The problem of all "dont-care" signal has solved (but there are another issues in your design) and the simulation results (see the attached image) seem to be as expected. (I use vcs instead of model-sim for the simulation.) The cause of having all dont-care signal is that there is an empty dff2 module in the file locker.v. The error is caught by the vcs compiler and the simulation looks good after the empty module been removed. However, I noticed that your design is asynchronous: the clock signal to trigger dff2 is generated by combinational logic and there may be un-expected glitches not found by the RTL simulation.
You can checkout my modified design through github by the commands:
git fetch origin
git checkout ycma_lab02
Please stand by my office if you have any further questions.
Sincerely,
Yung-Cheng
[image: shower_waveform.png]
On Sun, Oct 6, 2019 at 3:24 PM AiDSl notifications@github.com wrote:
I`m B0729004,I am now encounter the problem on 2bit memory, I firstly test my locker module and it fail;
To curect my mistake,I create the simple circuit called "samer_checker", although directly use samer is ok but fail at memory unit;
lastly,i directly test memory unit,it works ok, however it can`t be reproduce in other 2 module.
Repository: https://github.com/AiDSl/B0729004_CompOrg
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I`m B0729004,I am now encounter the problem on 2bit memory, I firstly test my locker module and it fail;
To curect my mistake,I create the simple circuit called "samer_checker", although directly use samer is ok but fail when combine memory unit;
lastly,i directly test memory unit,it works ok in waveform, however it can`t be reproduce in other 2 module
Here`s my Repository: https://github.com/AiDSl/B0729004_CompOrg