Fix machine outlining for CHERIoT

[resistor]

As an embedded platform, we would very much like to reap the code size benefits of MachineOutliner. However, for the moment MachineOutliner is disabled for CHERIoT, as it does not interact well with the backwards sentries used for call/return on CHERIoT. Specifically:

• The MachineOutliner uses ct0 as a scratch register, both to materialize the outlined function address prior to the call, as well as to hold the return address for the duration of the call to the outlined function. The outlined outlined function then returns through ct0 back to the original function. Notice that this does not use cra, the normal link register.
• In CHERIoT, any cjal or cjalr instruction that produces a link output, regardless of what register it writes to, always produces a backward sentry otype.
• The function return variant of cjalr used in the outlined function expects a different otype based on the source register used: for cra it expects a sealed backward sentry, but for all other registers it expects a sealed forward sentry.

Unfortunately, there's no simple way to fix this. A few options are:

• Restrict outlining to only cases where cra is dead so we can scavenge it.
• Restrict outlining to only produce outlined functions that end in tail calls
• Spill/restore the link register around the call to the outlined function, either to the stack or to another register that we scavenge.

The AArch64 backend actually implements all three of these strategies, as an optimization to attain minimal code size. It might make sense to port these strategies from AArch64 to RISCV in upstream, and then have CHERIoT bail out of outlining only when those strategies fail.

[resistor]

https://github.com/resistor/llvm-project-1/commit/05503ed587d1688fa46ef75513de70da7f145bbe

[davidchisnall]

See CHERIoT-Platform/cheriot-sail#85

[resistor]

On the CheriotRTOS test suite, re-enabling MachineOutlining reduces code size by approximately 4.4%