Investigate more aggressive MachineOutlining strategies

[resistor]

The AArch64 backend implements a number of different strategies for MachineOutliner which are used to reduce overhead / improve code size savings:

• Default - the outlined code uses a normal call sequence
• Tail call - the outlined code ends with a tail call
• No LR Save - the link register is known to be dead, so the save/restore can be skipped
• Thunk - the outlined code ends with a call to a normal function
• RegSave - the link register can be saved/restored to a scratch register rather than to the stack.

These are reasonably well explained in the upstream code here: https://github.com/llvm/llvm-project/blob/590f451b60d434b26c634a07125fb05baf461fa0/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp#L8570

The RISCV equivalent, by contrast, only implements the Default strategy today. Given that MachineOutliner provides significant code size savings for us, we should investigate porting some or all of the more advanced strategies from AArch64 to RISCV. Ideally this should be done in LLVM upstream, then cherry-picked and adapted for CHERIoT as needed.

[resistor]

Actually, the existing RISCV code does not implement the "Default" strategy, but rather a limited hybrid of RegSave and NoLRSave that uses X5 in place of the link register, failing if it's not available.

[resistor]

https://github.com/llvm/llvm-project/pull/117526

[davidchisnall]

See also CHERIoT-Platform/cheriot-sail#86, which should enable us to use the same outlining strategies as non-CHERI RISC-V.

[resistor]

https://github.com/llvm/llvm-project/pull/115297