uchobby
commented
7 years ago My mistake, had MOSI and MISO reversed. Sorry
The real problem is that it's not clear that the MISO and MOSI pins reverse when you put the port in Slave mode. In other words what is normally MOSI becomes MISO. You might naturally assume that the pin labels would stay the same, as I did.
Maybe this comment will help the next developer.
Tring the SPI test code with two ESP8266s connected, one as master and one as slave. Using the example code the specific interrupts like Master to Slave status is not occurring. A transfer interrupt is occurring on status transfers but none of the lower 4 bits of the status register are set.
For example, Master sends Status to Slave, Slave ISR is called with the transfer flag set but not the master sent status flag.
I assume some interrupt enables are missing as the test code ISR ends up only seeing the transfer flag.
I have verified that the Master is sending the SPI data in hardware using a logic analyzer, have even verified that the actual bytes are as expected. Just seems that the ESP is not setting the right bits.