Update Onyx port, Add Derecho intel port

[apcraig]

PR checklist

• [X] Short (1 sentence) summary of your PR: Update Onyx port, Add Derecho intel port
• [X] Developer(s): apcraig
• [X] Suggest PR reviewers from list in the column to the right.
• [X] Please copy the PR test results link or provide a summary of testing completed below. All tests pass, ran full test suites run on Onyx (3 compilers) and Derecho. No baselines to compare to at this time. https://github.com/CICE-Consortium/Test-Results/wiki/icepack_by_hash_forks#66de407dc88bd5a9189cd60ce31eb38deadd27c7, https://github.com/CICE-Consortium/Test-Results/wiki/icepack_by_hash_forks#df691e4ba1aa121e650ff69c93c4651ab9ef5850
• How much do the PR code changes differ from the unmodified code?
  • [X] bit for bit
  • [ ] different at roundoff level
  • [ ] more substantial
• Does this PR create or have dependencies on CICE or any other models?
  • [ ] Yes
  • [X] No
• Does this PR add any new test cases?
  • [ ] Yes
  • [X] No
• Is the documentation being updated? ("Documentation" includes information on the wiki or in the .rst files from doc/source/, which are used to create the online technical docs at https://readthedocs.org/projects/cice-consortium-cice/.)
  • [ ] Yes
  • [X] No, does the documentation need to be updated at a later time?
    • [ ] Yes
    • [X] No
• [ ] Please provide any additional information or relevant details below:

[apcraig]

Good catch, fixed.