Update Cheyenne and Derecho port

[apcraig]

PR checklist

• [X] Short (1 sentence) summary of your PR: Update Cheyenne and Derecho port
• [X] Developer(s): apcraig
• [X] Suggest PR reviewers from list in the column to the right.
• [X] Please copy the PR test results link or provide a summary of testing completed below. full test suites run on cheyenne, derecho, all tests pass and bit-for-bit except cheyenne pgi, https://github.com/CICE-Consortium/Test-Results/wiki/icepack_by_hash_forks#23b6c1272b50d42cad7928ffe0005d6ee673dee9
• How much do the PR code changes differ from the unmodified code?
  • [X] bit for bit except cheyenne pgi due to new compiler version
  • [ ] different at roundoff level
  • [ ] more substantial
• Does this PR create or have dependencies on CICE or any other models?
  • [ ] Yes
  • [X] No
• Does this PR add any new test cases?
  • [ ] Yes
  • [X] No
• Is the documentation being updated? ("Documentation" includes information on the wiki or in the .rst files from doc/source/, which are used to create the online technical docs at https://readthedocs.org/projects/cice-consortium-cice/.)
  • [ ] Yes
  • [X] No, does the documentation need to be updated at a later time?
    • [ ] Yes
    • [X] No

• [X] Please provide any additional information or relevant details below:

  All results are bit-for-bit except some pgi tests. All machine/compiler combinations pass all tests.

  Update cheyenne gnu, intel, pgi compiler version

  Minor update to Derecho intel

  Add Derecho cray, gnu, intelclassic, inteloneapi, nvhpc