DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is intended to study new architectures, such as near-data processing. Described by Oliveira et al. (preliminary version at https://arxiv.org/pdf/2105.03725.pdf)
Hey, I had some set of questions which I had doubt on, so could you help me upon it.
First doubt I had regarding the execution of offloadable and non-offloadble region when we run when pimmode=True. For example this line of execution: ./build/opt/zsim config_files/pim_ooo/stream/4/Add_Add.cfg
Correct me if I am wrong offloadable region under zsim readable tags execute in "4 PIM ooo cores" and the rest of the code which is non-offloadable region execute in HOST cores. So, here what is the count of HOST cores we are using to execute, and whether is it out-of-order or inorder??
My second doubt was regarding the configuration of this: template_pim_ooo.cfg: Defines a PIM system with multiple OOO cores and private L1 caches.
Its mentioned that PIM cores consist of private L1 cache and when i changed the code accordingly in config files and ran the code I am getting the below error. Could you please help me resolve this issue.
Hope, this message finds you and you could help me understand better, thank you!
Hey, I had some set of questions which I had doubt on, so could you help me upon it. First doubt I had regarding the execution of offloadable and non-offloadble region when we run when pimmode=True. For example this line of execution: ./build/opt/zsim config_files/pim_ooo/stream/4/Add_Add.cfg Correct me if I am wrong offloadable region under zsim readable tags execute in "4 PIM ooo cores" and the rest of the code which is non-offloadable region execute in HOST cores. So, here what is the count of HOST cores we are using to execute, and whether is it out-of-order or inorder?? My second doubt was regarding the configuration of this: template_pim_ooo.cfg: Defines a PIM system with multiple OOO cores and private L1 caches. Its mentioned that PIM cores consist of private L1 cache and when i changed the code accordingly in config files and ran the code I am getting the below error. Could you please help me resolve this issue.
Hope, this message finds you and you could help me understand better, thank you!