DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is intended to study new architectures, such as near-data processing. Described by Oliveira et al. (preliminary version at https://arxiv.org/pdf/2105.03725.pdf)
Hey, I had this doubt about why last level cache is required, can i not simulate the cores with private l1-d and l1-i cache itself?? what is the reason behind l3 cache requirement all the time in init.cpp at around lines 508??
is there a way and could you suggest what i can change in init.cpp so that it accepts only l1 cache not necessary to have last level cache to simulate??
So as mentioned in read.me about pim cores having private l1 cache only. But due to the requirement of last level cache why is it that the miss rate of l3 cache is 0?? does it mean that the latency to access data in l3 is worse than dealing with main memory directly?? what is the latency to access hmc by pim and host config?
Hey, I had this doubt about why last level cache is required, can i not simulate the cores with private l1-d and l1-i cache itself?? what is the reason behind l3 cache requirement all the time in init.cpp at around lines 508?? is there a way and could you suggest what i can change in init.cpp so that it accepts only l1 cache not necessary to have last level cache to simulate?? So as mentioned in read.me about pim cores having private l1 cache only. But due to the requirement of last level cache why is it that the miss rate of l3 cache is 0?? does it mean that the latency to access data in l3 is worse than dealing with main memory directly?? what is the latency to access hmc by pim and host config?