Closed LOCKEDGATE closed 5 days ago
I think you want a new "adapter" module that takes the same inputs as ddr4_adapter, but outputs DFI signals (instead of Xilinx DDR4 PHY IP input signals).
The ddr_pipeline.v module controls the input signals of the adapter.
Depending on how you read data from DRAM (using DFI), you may need to modify readback_engine.v.
Thanks a lot, I'll try that.
Hello, I read in your paper "We issue DRAM commands to the Xilinx DDR3/4 PHY IP [370] over a low-level DFI interface." Then because the Xilinx DDR PHY interface does not support the DFI protocol, when using a controller with the DFI protocol, an adapter is needed to convert the DFI signal to the Xilinx DDR PHY signal, similar to converting dfi_cas_n---->mc_CAS_n, etc. Then I saw ddr4_adapter.v in your project. If I want to further implement my needs, which files should I refer to?