MQSim is a fast and accurate simulator modeling the performance of modern multi-queue (MQ) SSDs as well as traditional SATA based SSDs. MQSim faithfully models new high-bandwidth protocol implementations, steady-state SSD conditions, and the full end-to-end latency of requests in modern SSDs. It is described in detail in the FAST 2018 paper by Arash Tavakkol et al., "MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices" (https://people.inf.ethz.ch/omutlu/pub/MQSim-SSD-simulation-framework_fast18.pdf)
Found switch case error within process_new_user_request() in Simple Cache Mode.
Or it will show error message.
Found something missing In function GC_and_WL_Unit_Base::handle_transaction_serviced_signal_from_PHY(NVM_Transaction_Flash* transaction).
I think the corresponding transaction should be submitted before scheduling if the block manager can execute GC and WL due to following reasons:
(1) The transaction should be submitted or it won't be schedule.
(2) See 'GC_and_WL_Unit_Page_Level::Check_gc_required()', it did submit the gc_erase_tr transaction before scheduling.
Therefore, I append a line of code for submitting gc_wl_erase_tr transaction before scheduling.
Found switch case error within process_new_user_request() in
Simple Cache Mode. Or it will show error message.Found something missing In function
GC_and_WL_Unit_Base::handle_transaction_serviced_signal_from_PHY(NVM_Transaction_Flash* transaction).I think the corresponding transaction should be submitted before scheduling if the block manager can execute GC and WL due to following reasons: (1) The transaction should be submitted or it won't be schedule. (2) See 'GC_and_WL_Unit_Page_Level::Check_gc_required()', it did submit the gc_erase_tr transaction before scheduling.
Therefore, I append a line of code for submitting gc_wl_erase_tr transaction before scheduling.