A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combines a widely-used simulator for out-of-order and in-order processors (ZSim) with Ramulator, a DRAM simulator with memory models for DDRx, LPDDRx, GDDRx, WIOx, HBMx, and HMCx. Ramulator is described in the IEEE CAL 2015 paper by Kim et al. at https://people.inf.ethz.ch/omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf Ramulator-PIM is used in the DAC 2019 paper by Singh et al. at https://people.inf.ethz.ch/omutlu/pub/NAPEL-near-memory-computing-performance-prediction-via-ML_dac19.pdf
Why do you generate unfiltered memory trace for PiM?
In your Napel paper, you said you simulated NMP where core has L1 cache.
However, since your memory trace is generated unfiltered, cache size does not affect the zsim output at all.
I have verified that if you are using pim_trace mode, cache does not affect the trace output.
How did you simulate your NMP with L1 cache using this framework?
Hi
Why do you generate unfiltered memory trace for PiM? In your Napel paper, you said you simulated NMP where core has L1 cache. However, since your memory trace is generated unfiltered, cache size does not affect the zsim output at all. I have verified that if you are using pim_trace mode, cache does not affect the trace output.
How did you simulate your NMP with L1 cache using this framework?