A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combines a widely-used simulator for out-of-order and in-order processors (ZSim) with Ramulator, a DRAM simulator with memory models for DDRx, LPDDRx, GDDRx, WIOx, HBMx, and HMCx. Ramulator is described in the IEEE CAL 2015 paper by Kim et al. at https://people.inf.ethz.ch/omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf Ramulator-PIM is used in the DAC 2019 paper by Singh et al. at https://people.inf.ethz.ch/omutlu/pub/NAPEL-near-memory-computing-performance-prediction-via-ML_dac19.pdf
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trace file is not being generated , the cycle count shows zero #26
ramulator.active_cycles_0 0 # Total active cycles for level _0
ramulator.busy_cycles_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0
ramulator.serving_requests_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0
ramulator.average_serving_requests_0 -nan # The average of read and write requests that are served in this DRAM element per memory cycle for level _0
ramulator.active_cycles_0_0 0 # Total active cycles for level _0_0
ramulator.busy_cycles_0_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0
ramulator.serving_requests_0_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0
ramulator.average_serving_requests_0_0 -nan # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0
ramulator.active_cycles_0_0_0 0 # Total active cycles for level _0_0_0
ramulator.busy_cycles_0_0_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0
ramulator.serving_requests_0_0_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0
ramulator.average_serving_requests_0_0_0 -nan # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0
ramulator.active_cycles_0_0_0_0 0 # Total active cycles for level _0_0_0_0
ramulator.busy_cycles_0_0_0_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0
ramulator.serving_requests_0_0_0_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0
ramulator.average_serving_requests_0_0_0_0 -nan # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0
ramulator.active_cycles_0_0_0_1 0 # Total active cycles for level _0_0_0_1
ramulator.busy_cycles_0_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1
ramulator.serving_requests_0_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1
ramulator.average_serving_requests_0_0_0_1 -nan # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1
ramulator.active_cycles_0_0_0_2 0 # Total active cycles for level _0_0_0_2
ramulator.busy_cycles_0_0_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2
ramulator.serving_requests_0_0_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2
ramulator.average_serving_requests_0_0_0_2 -nan # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2
ramulator.active_cycles_0_0_0_3 0 # Total active cycles for level _0_0_0_3
can anyone help me solve this issue as the trace with both pim as well as host the output of cycles is 0..
ramulator.active_cycles_0 0 # Total active cycles for level _0 ramulator.busy_cycles_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 ramulator.serving_requests_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 ramulator.average_serving_requests_0 -nan # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 ramulator.active_cycles_0_0 0 # Total active cycles for level _0_0 ramulator.busy_cycles_0_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 ramulator.serving_requests_0_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 ramulator.average_serving_requests_0_0 -nan # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 ramulator.active_cycles_0_0_0 0 # Total active cycles for level _0_0_0 ramulator.busy_cycles_0_0_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 ramulator.serving_requests_0_0_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 ramulator.average_serving_requests_0_0_0 -nan # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 ramulator.active_cycles_0_0_0_0 0 # Total active cycles for level _0_0_0_0 ramulator.busy_cycles_0_0_0_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 ramulator.serving_requests_0_0_0_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 ramulator.average_serving_requests_0_0_0_0 -nan # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 ramulator.active_cycles_0_0_0_1 0 # Total active cycles for level _0_0_0_1 ramulator.busy_cycles_0_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 ramulator.serving_requests_0_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 ramulator.average_serving_requests_0_0_0_1 -nan # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 ramulator.active_cycles_0_0_0_2 0 # Total active cycles for level _0_0_0_2 ramulator.busy_cycles_0_0_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 ramulator.serving_requests_0_0_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 ramulator.average_serving_requests_0_0_0_2 -nan # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 ramulator.active_cycles_0_0_0_3 0 # Total active cycles for level _0_0_0_3
can anyone help me solve this issue as the trace with both pim as well as host the output of cycles is 0..