A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combines a widely-used simulator for out-of-order and in-order processors (ZSim) with Ramulator, a DRAM simulator with memory models for DDRx, LPDDRx, GDDRx, WIOx, HBMx, and HMCx. Ramulator is described in the IEEE CAL 2015 paper by Kim et al. at https://people.inf.ethz.ch/omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf Ramulator-PIM is used in the DAC 2019 paper by Singh et al. at https://people.inf.ethz.ch/omutlu/pub/NAPEL-near-memory-computing-performance-prediction-via-ML_dac19.pdf
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How to to generate traces using `timing.core` or `simple.core`? #30
Has anyone attempted to generate traces using timing.core or simple.core, or to build a PIM architecture based on these cores? If so, I would greatly appreciate any insights or suggestions.
I am looking to build a PIM architecture using timing.core or simple.core instead of ooo.core and subsequently generate memory access traces.
Any guidance, references to similar projects, or detailed steps on how to approach this modification would be extremely helpful. Thank you!
Has anyone attempted to generate traces using
timing.coreorsimple.core, or to build a PIM architecture based on these cores? If so, I would greatly appreciate any insights or suggestions.I am looking to build a PIM architecture using
timing.coreorsimple.coreinstead ofooo.coreand subsequently generate memory access traces.Any guidance, references to similar projects, or detailed steps on how to approach this modification would be extremely helpful. Thank you!