A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
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multi-core simulation has a problem in handling writebacks for cache filtered mode #119
By defining the Write handling parameters in the
Trace::get_filtered_request
as static:
static bool has_write = false;static long write_addr;static int line_num = 0;
only one copy exists across all instances and hence the write requests are leaked/intermingled among cores.
To fix this problem, I replaced these three parameters by maps as follows:
By defining the Write handling parameters in the
Trace::get_filtered_requestas static:static bool has_write = false;static long write_addr;static int line_num = 0;only one copy exists across all instances and hence the write requests are leaked/intermingled among cores.
To fix this problem, I replaced these three parameters by maps as follows:
static std::map<Trace*,bool> has_write;static std::map<Trace*,long> write_addr;static std::map<Trace*,int> line_num;Thanks, Mohamed