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CMU-SAFARI / ramulator2

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
https://arxiv.org/abs/2308.11030
MIT License
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m_internal_prefetch_size for LPDDR5 #15

Open tongCIX opened 1 year ago

tongCIX commented 1 year ago

Could you please explain the m_internal_prefetch_size here? DDR5 has 16, however LPDDR has 8?

RichardLuo79 commented 10 months ago

Hi,

m_internal_prefetch_size refer to how much data are fetched for burst RD/WR operation of the DRAM chip (in the units of the channel width). This is used to calculate the amount of bytes that are transferred for one transaction:

int tx_bytes = m_dram->m_internal_prefetch_size * m_dram->m_channel_width / 8;

For example, DDR4 has internal_prefetch_size of 8, then a rank of DRAM chips will fetch 8 * 64 bits of data from the array for an RD/WR. These data will be sent in 8 bursts.

DRAM standards introduce higher internal prefetch size to bridge the gap between the slow memory core array and fast I/O. More information can be found here: https://www.synopsys.com/blogs/chip-design/ddr-generations-memory-density-speed.html

https://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory#DDR_SDRAM_prefetch_architecture