We believe this is a definition that may cause LPDDR5 spec illegal with respect to CAS Sync. How about a new definition at the rank level?

[najun-auto]

      m_preqs[m_levels["bank"]][m_commands["RD16"]] = [] (Node* node, int cmd, int target_id, Clk_t clk) {
        switch (node->m_state) {
          case m_states["Closed"]: return m_commands["ACT-1"];
          case m_states["Pre-Opened"]: return m_commands["ACT-2"];
          case m_states["Opened"]: {
            if (node->m_row_state.find(target_id) != node->m_row_state.end()) {
              Node* rank = node->m_parent_node->m_parent_node;
              if (rank->m_final_synced_cycle < clk) {
                return m_commands["CASRD"];  // CASRD
              } else {
                return cmd;``

The JEDEC specification requires RD to appear in the cycle(+1) immediately following CASRD and WR in the cycle(+1) immediately following CASWR, but the above definition does not result in that.

What about the idea of adding a new definition at the rank level to put CASRD+RD, CASWR+WR in the m_preqs queue?

[RichardLuo79]

Hi,

Thanks for the suggestion. We will look into this.