Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
Hi
I hope you're doing well. I'm working with Ramulator2 and I'm looking for information on the source of LPDDR5 timing parameters. Could you point me to the data source or relevant documentation for LPDDR5 timings?
Thanks for your time and assistance. Appreciate your work on the project.
Hi I hope you're doing well. I'm working with Ramulator2 and I'm looking for information on the source of LPDDR5 timing parameters. Could you point me to the data source or relevant documentation for LPDDR5 timings? Thanks for your time and assistance. Appreciate your work on the project.