Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
Dear Author,
While conducting a single core sequential memory read-only test on LPDDR5 6400, I noticed that the system bandwidth is constrained by cache performance with all default settings, rather than by the DRAM. Only when I modify the Cache latency to 1, I can find the effect of different memory bandwidth configurations. I want to know why it happens since it is not likely to be cache bound in the real system to do such a test.
Dear Author, While conducting a single core sequential memory read-only test on LPDDR5 6400, I noticed that the system bandwidth is constrained by cache performance with all default settings, rather than by the DRAM. Only when I modify the Cache latency to 1, I can find the effect of different memory bandwidth configurations. I want to know why it happens since it is not likely to be cache bound in the real system to do such a test.