Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
1- I am trying to understand the stats of ramulator2, to estimate the total BW of the running trace in SimpleO3 mode.
Could you please give some hints on that?
("total_num_read_requests + total_num_write_requests")*(tx_bytes)/(??)
2- I expected to see the same value for "total_num_read_requests + total_num_write_requests" and "llc_write_misses +llc_read_misses" but it seems they are not the same, so I wonder why not?
Are the llc_req and mem_req in the same size (tx_bytes)?
3- these two stats "memory_access_cycles_recorded_core_0" and "cycles_recorded_core_0" are unclear.
4- "memory_access_cycles_recorded_core_0" is not only related to the memory_access delay, as in some cases with the same number of memory requests (total_num_read_requests + total_num_write_requests), but with a different number of "num_expected_insts", the "memory_access_cycles_recorded_core_0" will not remain the same!
Hi,
1- I am trying to understand the stats of ramulator2, to estimate the total BW of the running trace in SimpleO3 mode. Could you please give some hints on that? ("total_num_read_requests + total_num_write_requests")*(tx_bytes)/(??)
2- I expected to see the same value for "total_num_read_requests + total_num_write_requests" and "llc_write_misses +llc_read_misses" but it seems they are not the same, so I wonder why not? Are the llc_req and mem_req in the same size (tx_bytes)?
3- these two stats "memory_access_cycles_recorded_core_0" and "cycles_recorded_core_0" are unclear. 4- "memory_access_cycles_recorded_core_0" is not only related to the memory_access delay, as in some cases with the same number of memory requests (total_num_read_requests + total_num_write_requests), but with a different number of "num_expected_insts", the "memory_access_cycles_recorded_core_0" will not remain the same!
Thanks,