Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
Hi, in your SimpleO3 llc.cpp, each cache miss will issue a single read. So I assume each read is a 64 bytes read. However, I find that in many DDR configuration DQ = 16 and BL =16. So the read length should be 16 * 16 / 8 = 32 bytes. So I want to ask how does it guarantee each read is 64 bytes.
Hi, in your SimpleO3 llc.cpp, each cache miss will issue a single read. So I assume each read is a 64 bytes read. However, I find that in many DDR configuration DQ = 16 and BL =16. So the read length should be 16 * 16 / 8 = 32 bytes. So I want to ask how does it guarantee each read is 64 bytes.