Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
Setup
Using a sample configuration script with a SPEC CPU2006 trace:
MemorySystem: impl: GenericDRAM clock_ratio: 3
DRAM: impl: LPDDR5 org: preset: LPDDR5_4Gb_x16 timing: preset: LPDDR5_6400
Controller: impl: Generic Scheduler: impl: FRFCFS RefreshManager: impl: AllBank RowPolicy: impl: OpenRowPolicy cap: 4 plugins:
AddrMapper: impl: RoBaRaCoCh