Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
I have integrated Ramulator2 as the back-end memory simulator of the Gem5. I need 8 channels of DDR4 3200, each with 25.6 GB/s bandwidth. Ramulator's Gem5 wrapper is connected to a memside port of the membus crossbar of the GEM5, with ~102.4GB/s bandwidth for each memside port.
One way to implement this, as the default implementation behaviour, is to handle the channel concept on the Ramulator side, which is to set the number of memory channels to 1 in the GEM5, and set the number of channels in the Ramulator's config file to 8. However, because in this implementation there will be only 1 memside port connected to the Ramulator, the memory bandwidth will be limited by ~102.4GB/s, much less than 8 x 25.6 = 204 GB/s of 8 DDR4 3200 channels.
The correct implementation is to handle memory channels on the Gem5 side by having 8 memside ports of membus connected to 8 instances of the Ramulator, each configured by 1 channel. With this implementation, I get this error:
RuntimeError: logger with name 'Ramulator::GenericDRAMSystem' already exists
Another concern with this approach is address mapping. The memory config (configs/common/MemConfig.py) default behaviour of GEM5 has this line of code:
` # The default behaviour is to interleave memory channels on 128
byte granularity, or cache line granularity if larger than 128
# byte. This value is based on the locality seen across a large
# range of workloads.
intlv_size = max(opt_mem_channels_intlv, system.cache_line_size.value)`
which means that it uses the LSBs for channel interleaving, which is compatible with the RoBaRaCoCh address mapper. What if we need to use other address mapping schemes?
Hi everyone,
I have integrated Ramulator2 as the back-end memory simulator of the Gem5. I need 8 channels of DDR4 3200, each with 25.6 GB/s bandwidth. Ramulator's Gem5 wrapper is connected to a memside port of the membus crossbar of the GEM5, with ~102.4GB/s bandwidth for each memside port.
One way to implement this, as the default implementation behaviour, is to handle the channel concept on the Ramulator side, which is to set the number of memory channels to 1 in the GEM5, and set the number of channels in the Ramulator's config file to 8. However, because in this implementation there will be only 1 memside port connected to the Ramulator, the memory bandwidth will be limited by ~102.4GB/s, much less than 8 x 25.6 = 204 GB/s of 8 DDR4 3200 channels.
The correct implementation is to handle memory channels on the Gem5 side by having 8 memside ports of membus connected to 8 instances of the Ramulator, each configured by 1 channel. With this implementation, I get this error:
RuntimeError: logger with name 'Ramulator::GenericDRAMSystem' already existsAnother concern with this approach is address mapping. The memory config (configs/common/MemConfig.py) default behaviour of GEM5 has this line of code:
` # The default behaviour is to interleave memory channels on 128
byte granularity, or cache line granularity if larger than 128
which means that it uses the LSBs for channel interleaving, which is compatible with the RoBaRaCoCh address mapper. What if we need to use other address mapping schemes?
I appreciate your help,