Closed peter-campora closed 5 months ago
Conditional pytket gates like:
circuit.X(data[0], condition=reg_eq(syndrome, 1)) circuit.X(data[0], condition=reg_eq(syndrome, 2))
cause unnecessary empty branches to be generated in the LLVM like:
then7: ; preds = %continue6 call void @__quantum__qis__phasedx__body(double 0x400921FB54442D18, double 0.000000e+00, %Qubit* inttoptr (i64 7 to %Qubit*)) br label %continue9 else8: ; preds = %continue6 br label %continue9 continue9: ; preds = %else8, %then7 %88 = call i1 @read_bit_from_reg(i64 %2, i64 5) br i1 %88, label %then10, label %else11
It would help program performance if these empty branches were removed.
We could use this with a llvm pass after the qir is generated.
@peter-campora is this still something we want to to here? From my understanding we could close this issue?
Done
Conditional pytket gates like:
cause unnecessary empty branches to be generated in the LLVM like:
It would help program performance if these empty branches were removed.