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CQCL / pytket-qir

Public repo for the pytket-qir package
Apache License 2.0
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Simplify Equality Checks #51

Closed peter-campora closed 1 year ago

peter-campora commented 1 year ago

Conditional gates are causing a complex series of operations to be generated in the QIR via 3 instructions where one equality operation would suffice.

For example, code like:

circuit.X(data[0], condition=reg_eq(syndrome, 1))

generates a series of instructions to generate the condition bit as follows:

  %9 = icmp sgt i64 1, %1
  %10 = icmp sgt i64 %1, 1
  %11 = and i1 %9, %10
  call void @set_one_bit_in_reg(i64 %2, i64 0, i1 %11)

It would reduce register pressure if this was replaced with the following:

  %9 = icmp eq i64 1, %1
  call void @set_one_bit_in_reg(i64 %2, i64 0, i1 %9)
cqc-melf commented 1 year ago

Solved in https://github.com/CQCL/pytket-qir/pull/52