VARI ESERCIZI DI VERILOG

[notedo]

[alem1105]

module es1(input logic a, clk, output logic y0, y1);
        always_ff @(posedge clk)
            begin
                y0 <= a;
                y1 <= ~a;
            end
endmodule

//---------------------------------------------//

module es2(input logic clk, en, reset, a, output logic y);
    // faccio un FF D
    always_ff @(posedge clk or posedge reset)
        if (reset) y <= 1'b0;
        else if (en) y <= a;
endmodule

//---------------------------------------------//

module es3(input logic a, b, c, output logic y);
    always_comb
        case ({b,a,c})
            3'b001: y = c;
            3'b011: y = 1'b1;
            3'b101: y = 1'b0;
            3'b111: y = a ^ b;
            default: y = a & b;
        endcase
endmodule

//---------------------------------------------//

module es4(input logic t, reset, clk, output logic y);
    always_ff @(posedge clk or posedge reset)
        if (reset) y <= 1'b0;
        else y <= t ^ y;
endmodule

//---------------------------------------------//

module buffer_tristate();
    //non so che e' :)
endmodule

//---------------------------------------------//

module es6(input logic clk, reset, output logic [3:0] value);
    //forse va begin
    always_ff @(posedge clk)
        if (reset): value <= 4'b0000;
        else if (count == 4'b1100): value <= 4'b0000;
        else count <= count + 1;
    //forse va end
endmodule