PSD #4 - 7 Giugno 2022

[rimaout]

[alem1105]

module es(input logic clk, enable, reset, x, output logic q);
    begin
        always_ff @(posedge clk or posedge reset);
            if (reset) q <= 1'b0;
            else if (enable) q <= x;
    end
endmodule