Lit Test for graph transformations #92

[Quincunx271]

The bug in #92 has a rather small test case which should be made into a lit regression test. The example DDG:

The def/use information:

LiveIn { R0, R1, R2, R3 }
a. COPY         Def{ R6 } Use{ R0 }
b. LEA64r(0)    Def{ R4 } Use{ R2, R3 }
c. LEA64r(1)    Def{ R5 } Use{ R1, R2 }
LiveOut{ R1, R3, R4, R5, R6 }

Buggy graph transformations result in a DDG of:

However, the optimal schedule is COPY first, as it closes the live range for R0.

[kerbowa]

You could try using LLVM's "-stop-before=machine-scheduler" -o file.mir <file> and then create a reduced version of the MIR based on that.

There don't seem to be many examples of MIR tests for X86 in LLMV either. I tried to make something to get you started since MIR is really finicky. For example you can only explicitly mark physical registers as livein...

This probably isn't recreating the register classes correctly to repo the bug. You can run the scheduler on this code at least with llc -march=x86-64 -run-pass=machine-scheduler testname.mir -o -.

---
name: testname                                                                                                                                                                                      
tracksRegLiveness: true

body:             |
  bb.0:
    %0:gr32 = IMPLICIT_DEF
    %1:gr64 = IMPLICIT_DEF
    %2:gr64_nosp = IMPLICIT_DEF
    %3:gr64_nosp = IMPLICIT_DEF
    JMP_1 %bb.1

  bb.1:
    %6:gr32 = COPY %0
    %4:gr32 = LEA64_32r %2, 0, %3, 0, $noreg
    %5:gr32 = LEA64_32r %1, 0, %2, 0, $noreg
    JMP_1 %bb.2

  bb.2:
    RET 0, implicit %1, implicit %3, implicit %4, implicit %5, implicit %6 

...