search

CTSRD-CHERI / QuickCheckVEngine

A RISC-V TestRIG Verification Engine based on QuickCheck
BSD 2-Clause "Simplified" License
7 stars 10 forks source link

Add RVC HINT/RES/NSE encs & rework disassembly #56

Open elliotb-lowrisc opened 2 months ago

elliotb-lowrisc commented 2 months ago

Add explicit HINT, Reserved, and NSE compressed instruction encodings from the spec. This allows Templates to more easily specify these special encodings and enables more accurate disassembly. Note that some encodings overlap.

Add new instruction disassembly pretty printer functions for special cases where the operands are uninteresting or ambiguous.

Rework the disassembly to account for overlapping encodings. Use XLEN, when available, and carful ordering to distinguish overlapping encodings from each other. Present both encodings when encodings overlap and XLEN is not available.

Integrate new disassembly so that XLEN will be passed through when known (currently only for RVFI V2 packets).

Minor errors may remain. Caution only goes so far when there are so many fiddly changes required.

elliotb-lowrisc commented 2 months ago

No tests currently use the new instructions, but you can try out the new disassembly using something like:

make QCVEngine
utils/scripts/runTestRIG.py -a sail -b sail -r rv32ic --test-include-regex "^compress" -v3 -n2

Note that a generic disassembly will be used for the plain instruction listing at the end, but a more precise (XLEN-aware) disassembly will be output when the RVFI packets are being compared.

elliotb-lowrisc commented 2 months ago

@PeterRugg I'm not sure how this fits in with your ongoing work, but hopefully it can be of some use.