Make the CHERI exception codes architecture-specific.

[bsdjhb]

Move the tables out of the architecture chapter and into each architecture spec. Morello already uses a different scheme for reporting exceptions that doesn't follow this code.

For RISC-V I moved the description of xtval out into a new subsection next to exception handling rather than being buried in a section about new CSRs.

For both RISC-V and x86-64 I have kept the existing values, but have condensed the tables slightly since they otherwise float several pages away.

[bsdjhb]

Note that unaligned base is not listed in the exception priority for RISC-V.

One other thought is that Morello uses far fewer exception codes. It has a single "Permission" fault that reports any permission fault rather than separate codes per permission. Morello is also missing the "Type" violation fault it seems.

For x86 I'd like to compress the values down to reclaim some of the gaps, but I'm also considering if a single "Permission" code is sufficient in practice (the si_code values we report to userland just use a single code for all permission faults).

[PeterRugg]

All looks good. Happy to add the unaligned_base priority once this is merged.