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CTSRD-CHERI / cheri-specification

CHERI ISA Specification
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Interconnect support for RISC-V AMOSWAP.C #67

Open andresag01 opened 1 year ago

andresag01 commented 1 year ago

The CHERI specification has the instruction AMOSWAP.C to atomically swap a capability in memory. Supporting this operation requires having a memory interconnect that atomically swap 16 bytes in RV64.

Many systems rely on AMBA AXI-5 protocol for their interconnect. AXI-5 has an atomic extension to support these features, but the AMBA specification indicates that atomic swap supports 1, 2, 4 and 8 byte outbound data sizes -- 16 bytes are not supported.

It is not ideal that AMOSWAP.C relies on a feature that conflicts with the current AXI-5 requirements for atomic swap. Are there currently any proposals to reconcile this conflict? Is AMOSWAP.C a critical instruction for CHERI given that it is possible to emulate its function (e.g. LR/SC)?

jrtc27 commented 1 year ago

Having AMOs for integers but not capabilities would unfairly penalise CHERI with code bloat and worse performance under contention due to LR/SC not scaling well

andresag01 commented 1 year ago

Agreed. However, I have not seen any data to assess whether that is a problem or not. Are you aware of any performance results? Also, I am not necessarily advocating for the instruction to be removed, for example, we could seek clarification on the AMBA AXI-5 spec -- it is not immediately clear why there is an 8-byte limit on atomic swap (perhaps cost concerns?).