Closed jinningwang closed 3 years ago
Merging #182 (faeddd6) into develop (711f01b) will decrease coverage by
0.19%
. The diff coverage is58.01%
.
@@ Coverage Diff @@
## develop #182 +/- ##
===========================================
- Coverage 78.76% 78.57% -0.20%
===========================================
Files 110 112 +2
Lines 12036 12176 +140
===========================================
+ Hits 9480 9567 +87
- Misses 2556 2609 +53
Impacted Files | Coverage Δ | |
---|---|---|
andes/models/__init__.py | 100.00% <ø> (ø) |
|
andes/models/exciter/esst1a.py | 21.42% <21.42%> (ø) |
|
andes/models/exciter/__init__.py | 100.00% <100.00%> (ø) |
|
andes/models/exciter/ac8b.py | 100.00% <100.00%> (ø) |
|
andes/models/exciter/esac1a.py | 100.00% <100.00%> (ø) |
|
andes/models/exciter/excbase.py | 100.00% <100.00%> (ø) |
|
andes/models/exciter/ieeet3.py | 100.00% <100.00%> (ø) |
|
andes/core/block.py | 83.30% <0.00%> (+0.35%) |
:arrow_up: |
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Good idea to separate them.
Okay, will we fix the LVGate
error?
I haven't explored it yet.
I’m not sure about the issue. I can look at it tomorrow. On Sep 28, 2021, 11:18 PM -0500, Jinning Wang @.***>, wrote:
Okay, will we fix the LVGate error? I haven't explored it yet. — You are receiving this because you commented. Reply to this email directly, view it on GitHub, or unsubscribe.
Kudos, SonarCloud Quality Gate passed!
1) Added
ExcVsum
to refactor exciters. 2) RefactoredAC8B
andIEEET3
. 3) FixedAC8B
initialization error. 4) DevelopedESAC1A
.Bug reported: Series
HVGate
andLVGate
will result in an initialization error inLVGate
. So I useLimiter
to avoid it.