With the new version of PROLEAD supporting assign statements, removing buffers in the synthesized file is advantageous. The updated script eliminates inserted buffers and removes unused cells and wires from the synthesized output generated by Yosys. This enhancement decreases execution time and memory usage, particularly for large designs.
With the new version of PROLEAD supporting
assignstatements, removing buffers in the synthesized file is advantageous. The updated script eliminates inserted buffers and removes unused cells and wires from the synthesized output generated by Yosys. This enhancement decreases execution time and memory usage, particularly for large designs.