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基本寄存器设计实验 | Clerk.Max(well); #58

Open Chaos-xBug opened 2 years ago

Chaos-xBug commented 2 years ago

https://lht.wiki/20211210-DC-reg/

基本寄存器设计实验实验原理 实验步骤 实验代码123456789101112131415161718`timescale 1ns / 1psmodule register8D(OE, CLR, CLK, D, Q); input OE_, CLR, CLK; input [7:0]D; output [7:0]Q; reg [7:0]A; always @(pos

lhtxd commented 2 years ago

吕桑，多给点注释滴干活

Chaos-xBug commented 2 years ago

@lhtxd 吕桑，多给点注释滴干活

下次一定

WenzheXie commented 2 years ago

汀桑，之前说基本寄存器哪里需要修改啊

Chaos-xBug commented 2 years ago

@WenzheXie 汀桑，之前说基本寄存器哪里需要修改啊

太君，小的已经改好了滴干活