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Charmve / AccANN

🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*
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Source Code is missing #3

Open dentionY opened 1 year ago

dentionY commented 1 year ago

Hello, I am interested in your code and want to have a try! However, I can not find the source code! Welcome for your relpy, thank you!