Verilog Tutorial Notes

[Chen-Gary]

端口连接规则

输入端口

模块例化时，从模块外部来讲， input 端口可以连接 wire 或 reg 型变量。这与模块声明是不同的，从模块内部来讲，input 端口必须是 wire 型变量。

输出端口

模块例化时，从模块外部来讲，output 端口必须连接 wire 型变量。这与模块声明是不同的，从模块内部来讲，output 端口可以是 wire 或 reg 型变量。

输入输出端口

模块例化时，从模块外部来讲，inout 端口必须连接 wire 型变量。这与模块声明是相同的。

(ref: https://www.runoob.com/w3cnote/verilog-generate.html)

[Chen-Gary]

All the statements inside the always block execute sequentially. Further, if the module contains more than one always block, then all the always blocks execute in parallel, i.e. always blocks are the concurrent blocks.

4.6.1. ‘always’ block for ‘combinational designs’

Follow the below rules for combinational designs,

• Do not use the ‘posedge’ and ‘negedge’ in sensitive list.
• Sensitive list should contain all the signals which are read inside the block.
• No variable should be updated outside the ‘always’ block.
• Use blocking assignment (i.e. = ) for assigning values.
• All the variables should be updated for all the possible input conditions i.e. if-else and case statements should include all the possible conditions; and all the variables must be updated inside all the conditions.

4.6.3. ‘always’ block for ‘sequential designs’

Follow the below rules for sequential designs,

• Use either ‘posedge’ or ‘negedge’ (not both) in sensitive list for all the elements.
• No variable should be updated outside the ‘always’ block.
• Use non-blocking assignment (i.e. <= ) for assigning values.

(ref: https://verilogguide.readthedocs.io/en/latest/verilog/procedure.html)

[Chen-Gary]

Delays in Verilog

In Verilog, without explicit specification of such constraints, the outputs of pre-defined primitives and user-defined modules are all assumed to resolve instantaneously (or at least, within one simulator timestep).

(ref: https://athena.ecs.csus.edu/~changw/class_docs/VerilogManual/delays.html)