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Chen-Gary / CPU-verilog

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Questions #2

Closed Chen-Gary closed 3 years ago

Chen-Gary commented 3 years ago

The following questions are all solved

  1. How to implement WB? Wait for the posedge? Internal forwarding?

    Use #2 (delay).

  2. How to deal with PC?

    Start from 0.

  3. How to use the two provided modules

  4. The question about posedge-triggered (in OneNote)

  5. How to determine clock width?

    Arbitrary.

Chen-Gary commented 3 years ago

ID_stage: initialize register file?

initialize to all 0

There is no problem encountered so far. "Initialize to all 0" can work.