Chen-Gary / CPU-verilog

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Closed Chen-Gary closed 3 years ago

Chen-Gary commented 3 years ago

[x] Note that all the outputted control signals in each stage should be initialized to 0 (by using initial block)

Chen-Gary commented 3 years ago

Other:

[x] your CPU should display the top 30 rows of the Main Memory in the screen.
[x] the strategy to end your program is at the point where your CPU execute 32'hffffffff instruction
[x] draw the circuit graph based on your design logic in your report
[x] record the number of clock cycles your CPU used to execute these testing samples

Chen-Gary commented 3 years ago

DONE. Yes, we need to flush.

Need to flush when branch and jump?

Implementation:

flush ID and EX stage with one additional flush control signal

In the pipeline register submodule, wait #1 for the flush signal, and then set the sequential read-in variables to 0

Chen-Gary commented 3 years ago

Use this to implement register file:

reg [31:0] DATA_RAM [0:512-1];

Chen-Gary commented 3 years ago

Please do not always change the requirements at the last minute!

[x] please output the whole memory to the terminal or to a file
[x] we will use your testbench module and an instruction file named "instructions.bin" to test your project. Please set the input file name as above in your project