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ChillyTheDev / Capstone

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Parallel Block Implementation #3

Closed ChillyTheDev closed 4 years ago

ChillyTheDev commented 4 years ago

Setup a modular FFT which uses the parallel block style implementation. This implementation will require modular butterfly sum blocks and memory accessing. Start with completing an 8-point FFT which is the first size that requires complex multiplication.

ChillyTheDev commented 4 years ago

An individual complex multiplier requires 4 hardware multipliers which is already rather expensive. Each butterfly sum requires 2 complex multipliers which means 8 multipliers would be required in a single 2-point DFT block using the parallel model. So in a 8-point FFT (8/2)log2(8)8 =96 hardware multipliers would be required and this will continue to grow exponentially. A 16-point will require (16/2)log2(16)8 = 256 multipliers. Considering the Altera DE0-Nano only has 66 hardware multipliers and the DE2-115 has 266 this design architecture is simply not feasible.