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ChinaQMTECH / QM_XC7A100T_WUKONG_BOARD

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Move SYSCLK from M22 to M21 #1

Open rHermes opened 3 years ago

rHermes commented 3 years ago

Hey! I haven't recieved my board yet, but from looking at the schematics, I can see that you use M22 as the pin in for the system clock. This is suboptimal as it's not able to use the BUFMR primitive which allows for multi-region clocking. The reason for this is that you are using the slave side of a MRCC pin. Simply moving it to M21 would make this go away, especially as the pin is free.

Sources: https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf Page 105, quote:

very MRCC pin has a master or P-side and a slave or N-side. When using a MRCC pin to drive a BUFMR, use only the master or P-side. To identify the master or P-side, look for a P in the pin name (for example: IO_LxxP_Tx_MRCC_xx)

I don't know if you can change this at this stage, but I just thought I'd let you and anyone else thinking about this know.

Thanks for making these boards!

RndMnkIII commented 3 years ago

Hey! I haven't recieved my board yet, but from looking at the schematics, I can see that you use M22 as the pin in for the system clock. This is suboptimal as it's not able to use the BUFMR primitive which allows for multi-region clocking. The reason for this is that you are using the slave side of a MRCC pin. Simply moving it to M21 would make this go away, especially as the pin is free.

Sources: https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf Page 105, quote:

very MRCC pin has a master or P-side and a slave or N-side. When using a MRCC pin to drive a BUFMR, use only the master or P-side. To identify the master or P-side, look for a P in the pin name (for example: IO_LxxP_Tx_MRCC_xx)

I don't know if you can change this at this stage, but I just thought I'd let you and anyone else thinking about this know.

Thanks for making these boards! HI rHermes, I've successful tested the QMTECH Wukong Artix-7 with an 100MHz 64Mbit HyperRAM PMOD module using a 96MHz clock and double data ratio IDDR/ODDR primitives and passed a pattern RAM test at 96MHz generated from MMCM block lowering the signal strength in the memory side (register controllable), running it for more than eight hours without any error. I've used the following hyperram controller adapted for the Wukong board (basically change the external clock frequency and MMCM settings, change the FPGA part to xc7a100tfgg676-3, and change physical pin mapping, bitstream SPI settings): https://github.com/jorisvr/te0890-utils/tree/master/hyperram_test

SanadaShinken commented 3 years ago

Hello, @RndMnkIII :

I also have the same problem about M22 ping's usage. BTW, in what you provide project, it seems for Mesa Labs' Spartan7 M2 Board, not for Xilinx ARTIX-7 XC7A100T. There is no M22 pin about information in the project.

Is there any overwrite setting command?? BR, Sanada