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ChipFlow / mpw4

SoC and build scripts for MPW4
BSD 2-Clause "Simplified" License
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Overlapping DC block with routing wire #6

Closed FatsieFS closed 2 years ago

FatsieFS commented 2 years ago

@jpc-lip6 I have done locally a P&R. I do seem to see an overlap of the DC via blocks with a routing wire: DCWireOVL This shows only met1 layer. I did have one failed route though so I don't know if it is related.

FatsieFS commented 2 years ago

Seems to also happen on met2/met3/met4

FatsieFS commented 2 years ago

After updating the routing gauge to square via in #5 , I still get the overlapping DC connection block to the routing wires.

jpc-lip6 commented 2 years ago

Yes. I found the problem and corrected it. Not commited yet because the fix did trigger another bug that prevent the routing to complete.

I will commit the whole lot this evening or tomorrow once fully fixed.

gatecat commented 2 years ago

I think this can be closed now with the most recent Coriolis commits

FatsieFS commented 2 years ago

I rerun the PnR with latest Coriolis and latest version of StdCellLib and this issue seems to be solved.