ChrisShakkour / RV32I-MAF-project

Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
MIT License
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Latch and race condition detected, #39

Closed ChrisShakkour closed 2 years ago

ChrisShakkour commented 2 years ago

https://github.com/ChrisShakkour/RV32I-MAF-project/blob/56245e36953430c5530309f21c13b81a9a400a5c/temporary/register_file/RegisterFile.sv#L60

  1. Race when forwarding the input to the output we might create a race condition given the output is not flopped and might affect signals controlling the inputs of the register file.

  2. Latch always comb is not fully covered, if -> else if -> else if -> unknown when using an always block you need to make sure the signal is assigned a value at all times in all conditions, the else condition when none of the conditions hold. is not covered thus you won't see this on the testbench thinking it's ok because it generates a latch that holds the last value, but it's critical and not acceptable on any modern design, LATCH FREE DESIGN!

example rs1 address is 0x1 and rs1 read is Zero, the always block has no coverage for this case.