ChrisShakkour / RV32I-MAF-project

Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
MIT License
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set alu lsb bit zero for JALR and Branch commands, offset is always even. #55

Closed ChrisShakkour closed 2 years ago

ChrisShakkour commented 2 years ago

https://github.com/ChrisShakkour/RV32I-MAF-project/blob/35260c4be6706cbd190e29a5d8ce9a43b7423be2/HDL/rtl_src/core_top/core/Execute.sv#L19

ChrisShakkour commented 2 years ago

Done!