Open willdeacon opened 4 years ago
cc @kees
cc @kbeyls
https://llvm.org/pr46994 is an LLVM bug tracker issue covering implementing this. It currently seems unclear in how far this would actually improve hardening and, if implemented, if this would need to go under a different command line option to enable users to select which tradeoff they want on the hardening vs performance overhead impact.
I still think this is worth doing; though I don't understand why the GCC bug seems to be specific to ARM; wouldn't all architectures appreciate such protection, or was it simply that ARM backends had such a bug?
@nickdesaulniers To answer your question, yes, only the AArch64 backend had this issue, which was noticed during review of the RISC-V implementation.
@bwendling attempted this in https://github.com/llvm/llvm-project/pull/65461.
If I understand his message correctly, what @bwendling attempted is actually to clear the stack protector guard information located on the stack, not the register that held the stack guard value, which he is going to work on now.
@tsautereau-anssi That's correct. The other change may still be useful, but the register clearing is more important.
GCC bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96191 prompted me to look at clang's code generation for that testcase:
It appears that clang isn't zeroing the registers holding the stack canary at all. For example, in the prologue after loading into
x8
and in the epilogue after restoring intox8
and reloading the global canary intox9
.