[Enhancement] Add Readme and Help

[black-pudding]

Could it be possible to add more explanation of what this project is about? How and where this ultimate cartridge can be made or can be bought?

[ClusterM]

Yes, it's planned. I just can't find free time to do it.

[38293312]

The following message appears during compilation： Warning (10240): Verilog HDL Always Construct warning at mappers.vh(1026): inferring latch(es) for variable "irq_scanline_ready", which holds its previous value in one or more paths through the always construct Warning (10240): Verilog HDL Always Construct warning at mappers.vh(1026): inferring latch(es) for variable "irq_scanline_out", which holds its previous value in one or more paths through the always construct Warning (21074): Design contains 3 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "ppu_addr_in[0]" Warning (15610): No output dependent on input pin "ppu_addr_in[1]" Warning (15610): No output dependent on input pin "ppu_addr_in[2]" Warning (335093): TimeQuest Timing Analyzer is analyzing 2 combinational loops as latches. Critical Warning (332012): Synopsys Design Constraints File file not found: 'CoolGirl.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Warning (335093): TimeQuest Timing Analyzer is analyzing 2 combinational loops as latches. Critical Warning (332012): Synopsys Design Constraints File file not found: 'CoolGirl.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Critical Warning (332148): Timing requirements not met

[ClusterM]

Soon.