Closed Codax2000 closed 1 year ago
Current plan: 8:1 deserializer, on the following topology:
Problem with flip flops in testbench: _Q
values should match their previous generated values, but they don't
Slew gets worse and worse, is probably killing timing.
One possible solution: use standard flip flops or use Q_bar
out of the flip flops with a larger inverter to help with slewing
Use TSPC latches and flip flops to make a deserializer