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Colby-CPU-Sim / CPUSim

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Multi-byte "conditional" compilation #100

Closed Nava2 closed 7 years ago

Nava2 commented 7 years ago

The HC12 is a CISC architecture, thus has some requirements for compiling multiple addressing modes, for example:

adca

Currently, it looks as though all of these would need to be exposed by hand via: adca_imm, adca_dir, adca_ind etc.

I'm unsure if I am missing something to do this in the current model.

djskrien commented 7 years ago

You are not missing anything in the current model, which requires that each opcode have a unique name, a fixed instruction length, and a list of operands of fixed sizes. See also issue #35, which was created after trying to simulate the 6502. The way simulation was done in the case of the simulation of the 6502 was to expose it by hand, as you suggested.

Nava2 commented 7 years ago

I'm going to close this in favour of #35. This is literally the same problem since the 6502 definitely shares the same issue since its so similar to the 6809.