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ColinPitrat / caprice32

An emulator of the Amstrad CPC 8bit home computer range.
GNU General Public License v2.0
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Bad memory configuration - fix #221

Closed DSkywalk closed 2 years ago

DSkywalk commented 2 years ago

Hello Colin! :call_me_hand:

Yesterday we fixed this problem that freezes original release of Heroquest (CRC: EC279622), it's a bug that's been hiding there all these years: https://github.com/libretro/libretro-cap32/commit/467c4fefb7c861d14be88760ee421d99897e65d9

more info (in spanish sorry): https://twitter.com/dskywalk/status/1502938646785282050

Take care and best regards mate! :+1:

ColinPitrat commented 2 years ago

Thanks, very interesting!

I'll see if this solves some of the unsolvable issues I had :-)

From http://cpctech.cpc-live.com/docs/rampage.html

The ram paging register is accessed when bit 15 of I/O address is set to "0". This register is write only and cannot be read. This register shares the same I/O address decoding as the Gate-Array, but uses a unused function to avoid conflict.

To be compared with the Gate Array (https://www.cpcwiki.eu/index.php/Gate_Array):

The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

Though the Gate Array documentation mentions bits 6&7 set to 1 controlling the memory configuration, it seems to be incorrect. The Note does mention that it's handled by another chip but doesn't mention the different logic for the address:

This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464, CPC664 and KC compact, this function is performed in a memory-expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then the function is not available. In the CPC6128, this function is performed by a PAL located on the main PCB, or a memory-expansion. In the 464+ and 6128+ this function is performed by the ASIC or a memory expansion. Please read the document on RAM management for more information.

From https://www.cpcwiki.eu/index.php/I/O_Port_Summary and https://www.cpcwiki.eu/index.php/Default_I/O_Port_Summary confirms the right way to decode it is to check only at bit 15 being 0.

DSkywalk commented 2 years ago

Happy to read you Colin! :D

The biggest thanks go to @jcgamestoy, who helped and guided me when I detected the problem in order to solve it :tada:

You've documented it brilliantly, I'll add it to my next update. Best regards!!