improve docs

[mattvenn]

Hi! nice presentation at FSiC2023!

Please improve the docs by adding a simple example command that shows logic locking in action.

Also, I just tested the plugin with oss-cad-suite, which might be worth including in your 'install instructions' section as it's a lot faster to install yosys that way.

Thanks, Matt

[Coloquinte]

Thank you, that was quick! Good point! It's done for the README. I'll check oss-cad-suite. Would you have an example of adding a plugin to it?

[Coloquinte]

Added the link to oss-cad-suite :)

[mattvenn]

make and make install works after oss-cad-suite installed

[mattvenn]

If you want to tape out an example on TinyTapeout 04 I will give you a free slot.

[Coloquinte]

Thank you that's very nice !

[mattvenn]

where's a good place to ask questions about this? Is it possible to run this before synthesis? I'm thinkng the easiest way to tapeout would be add the logic locking, then write verilog. then run it through openlane.

Trying to run pre synth with this command:

yosys -m moosic-yosys-plugin -p 'read_verilog tt_um_seven_segment_seconds.v ; logic_locking -max-percent 5 -target corruption'

fails with:

2. Executing LOGIC_LOCKING pass.
Running logic locking with 10 test vectors, target 5.0% (0 cells out of 6).
ERROR: Assert `wire && wire->width == 1' failed in /opt/tabby/share/yosys/include/kernel/rtlil.h:1637.

tt_um_seven_segment_seconds can be found here: https://github.com/TinyTapeout/tt04-verilog-demo/blob/main/src/tt_um_seven_segment_seconds.v

[mattvenn]

maybe it's a good idea to include a full demo design with a makefile that runs the logic lock and gets an output bonus points for a github action that installs oss cad suite, compiles the plugin and runs a test automatically!

(inspiration: https://github.com/TinyTapeout/tt04-verilog-demo/actions/runs/5398183057/workflow)

[Coloquinte]

Indeed, it's only post-synthesis - I need to improve this error message. Difficult to do locking at the RTL level, since it's more difficult to get a logical model there. So usually I do synth then logic_locking. I think a verilog export and back to open lane should work?

Asking here on GitHub issues is fine. If you prefer, we can talk by email too :)

[mattvenn]

could you give an example yosys command?

this is failing post synth:

yosys -m moosic-yosys-plugin -p 'read_verilog tt_um_seven_segment_seconds.v decoder.v; synth -top tt_um_seven_segment_seconds; flatten; logic_locking -max-percent 5 -target corruption'

[Coloquinte]

This is a bug on my part on multi-bit module ports - all my benchmarks have single-bit ones :/ I'll get it fixed ASAP and get back to you once I get tinytapeout modules to work (probably tuesday next week as I'm on vacation until then).

[Coloquinte]

Hi Matt, I just pushed a fix, and the command for TinyTapeout is working now :) I opened a bunch of new issues to track the improvements I want to do in the close future. Don't hesitate to add new ones ;)

[mattvenn]

thanks!

On Thu, 13 Jul 2023 at 11:01, Gabriel Gouvine @.***> wrote:

Hi Matt, I just pushed a fix, and the command for TinyTapeout is working now :) I opened a bunch of new issues to track the improvements I want to do in the close future. Don't hesitate to add new ones ;)

— Reply to this email directly, view it on GitHub https://github.com/Coloquinte/moosic-yosys-plugin/issues/1#issuecomment-1633847370, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAE223F37AO5FSU226IUXX3XP62PFANCNFSM6AAAAAA2F45IBE . You are receiving this because you authored the thread.Message ID: @.***>

-- Matthew Venn web mattvenn.net twitter @matthewvenn https://twitter.com/matthewvenn

[Coloquinte]

Thank you for the feedback :) It's starting to look a bit robust to actual designs ;)