Closed Coloquinte closed 6 months ago
I solved it the hard way for hierarchical designs, which are now supported. There are still limitations to document when synthesis is not done
We should report when an unknown evaluable cell is present: that would take care of cells present before synth or in FPGA designs ($lut, $alu, ...).
We should at least have a useful error when the design is hierarchical or not synthetized