AFE 362/008 : Cal pulses only seen in A1 and A4.

[SeanCGriffin]

See plots in #148 .

Verified with a probe that pulses can be seen with an attenuator and verified with microscope that the ASIC pin looks OK (not shorted to adjacent pins). ASICs in question all passed QC charge injection.

[adamschoenwald]

From #148 before split, From Sean:

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ASIC Vthr_DAC = 1 for these tests. Readout is disabled so should just be looking at triggers.

AFE S/N 362/008: With probe: No trigger pulses on A5-06; pulses seen on A3-O6 but intermittent and not always in the same place (i.e noisy trigger??). Confirmed with scope that A5-06 has data during readout.

[SeanCGriffin]

Correcting ILA plot:

[adamschoenwald]

Check that the VTHR pin is not shorted to +1.5 or some other random value. Should match what is set on the internal DAC if not being over-ridden.

[adamschoenwald]

Alternate top side probe point

[SeanCGriffin]

[SeanCGriffin]

Measured with a probe; voltages are a BIT higher than expected as per the datasheet but not at the voltage rail.

e.g. Vthr_dac = 16 expects 96.6 mV, I measure about 110mV (on all channels). Vthr_dac = 32 expects 181.7 mV, measure about 205 mV

Checked for each ASIC on AFE008 and A0 on AFE018

[adamschoenwald]

Measure the mbias point shown in this figure. The mbias current will be i_mbias = (1.5 - Vmeasure) / 48.7e3 Amps. Compare this value on asics that are working properly vs ascis that are not triggering correctly.

[adamschoenwald]

Also verify the asics are actually in state 3 ( [s2,s1,s0] = [0,1,0]) by probing each line w/ the oscilloscope dc coupled. Expect +1.5V for a 1, -2.0V for a 0.

[SeanCGriffin]

I'll have a look. I think the states have to be working because data and config readout works but this is an easy check.

On Thu, Feb 11, 2021, 6:24 PM Adam Schoenwald notifications@github.com wrote:

Also verify the asics are actually in state 3 ( [s2,s1,s0] = [0,1,0]) by probing each line w/ the oscilloscope dc coupled. Expect +1.5V for a 1, -2.0V for a 0. [image: asic mode state lines] https://user-images.githubusercontent.com/6669107/107711881-64627380-6c96-11eb-9029-4263d796fd04.PNG [image: asic_state_logic] https://user-images.githubusercontent.com/6669107/107711889-66c4cd80-6c96-11eb-830f-6810e62a6a53.PNG

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[SeanCGriffin]

Confirmed ASICs in M3.

[SeanCGriffin]

Probed ASIC pins, triggered off of opposite side's cal pulse (hence the reflection)

[SeanCGriffin]

This is weird -- changing the test channel seems to have brought an ASIC back??

test_channel = 10:

test_channel = 18:

test_channel = 0: